# 100 MCQ on Computer Architecture For Competitive Exams

### Application Form 2020

Computer Architecture (CA) is one of the most scoring subjects in Competitive Exams. Those who score great in it stands higher on the merit. To help students, we have started a new series call “Computer Awareness for Competitive Exams”. In this post, our team has brought some of the well-compiled MCQ on Computer Architecture asked in Competitive Exams. These MCQ’s practice sets on Computer Architecture are the best way to check your computer knowledge before going for any competitive exams. Let us explore, the model paper on Computer Architecture.

## Set:- 1 MCQ on Computer Architecture

Instruction: From the four options, choose the most appropriate answer.

Marks: Each question carries 1 (one) mark (Total 100 marks)

1. In Reverse Polish notation, expression A*B+C*D is written as
(A) AB*CD*+ (B) A*BCD*+ (C) AB*CD+* (D) A*B*CD+
Ans: A

2. SIMD represents an organization that ______________.
(A) refers to a computer system capable of processing several programs at the same time.
(B) represents the organisation of a single computer containing a control unit, a processor unit and a memory unit.
(C) includes many processing units under the supervision of a common control unit
(D) none of the above.
Ans: C

3. Floating point representation is used to store
(A) Boolean values (B) whole numbers (C) real integers (D) integers
Ans: C

4. Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?
(A) 1 Megabyte/sec (B) 4 Megabytes/sec (C) 8 Megabytes/sec (D) 2 Megabytes/sec
Ans: D

5. Assembly language
(A) uses alphabetic codes in place of binary numbers used in machine language
(B) is the easiest language to write programs
(C) need not be translated into machine language
(D) None of these
Ans: A

6. In computers, subtraction is generally carried out by
(A) 9’s complement (B) 10’s complement (C) 1’s complement (D) 2’s complement
Ans: D

7. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to
(A) the time its takes for the platter to make a full rotation
(B) the time it takes for the read-write head to move into position over the appropriate track
(C) the time it takes for the platter to rotate the correct sector under the head
(D) none of the above
Ans: A

8. What characteristic of RAM memory makes it not suitable for permanent storage?
(A) too slow (B) unreliable (C) it is volatile (D) too bulky
Ans: C

9. Computers use addressing mode techniques for _____________________.
(A) giving programming versatility to the user by providing facilities as pointers to memory counters for loop control
(B) to reduce no. of bits in the field of instruction
(C) specifying rules for modifying or interpreting address field of the instruction
(D) All the above
Ans: D

10. The circuit used to store one bit of data is known as
(A) Register (B) Encoder (C) Decoder (D) Flip Flop
Ans: D

11. (2FAOC) 16 is equivalent to
(A) (195 084) 10 (B) (001011111010 0000 1100) 2 (C) Both (A) and (B) (D) None of these
Ans: B

12. The average time required to reach a storage location in memory and obtain its contents is called the
(A) seek time (B) turnaround time (C) access time (D) transfer time
Ans: C

13. Which of the following is not a weighted code?
(A) Decimal Number system (B) Excess 3-cod
(C) Binary number System (D) None of these
Ans: B

14. The idea of cache memory is based
(A) on the property of locality of reference (B) on the heuristic 90-10 rule
(C) on the fact that references generally tend to cluster (D) all of the above
Ans: A

15. Which of the following is lowest in memory hierarchy?
(A) Cache memory (B) Secondary memory (C) Registers (D) RAM (E) None of these
Ans: B

16. The addressing mode used in an instruction of the form ADD X-Y, is
(A) Absolute (B) indirect (C) index (D) none of these
Ans: C

17. If memory access takes 20 ns with cache and 110 ns without it, then the ratio ( cache uses a 10 ns memory) is
(A) 93% (B) 90% (C) 88% (D) 87%
Ans: B

18. In a memory-mapped I/O system, which of the following will not be there?
(A) LDA (B) IN (C) ADD (D) OUT
Ans: A

19. In a vectored interrupt.
(A) the branch address is assigned to a fixed location in memory.
(B) the interrupting source supplies the branch information to the processor through an interrupt vector.
(C) the branch address is obtained from a register in the processor
(D) none of the above
Ans: B

20. Von Neumann architecture is
(A) SISD (B) SIMD (C) MIMD (D) MISD
Ans: A

## Set:- 2 MCQ on Computer Architecture

21. The circuit used to store one bit of data is known as
(A) Encoder (B) OR gate (C) Flip Flop (D) Decoder
Ans: C

22. Cache memory acts between
(A) CPU and RAM (B) RAM and ROM (C) CPU and Hard Disk (D) None of these
Ans: A

23. Write Through technique is used in which memory for updating the data
(A) Virtual memory (B) Main memory
(C) Auxiliary memory (D) Cache memory
Ans: D

24. Generally, Dynamic RAM is used as main memory in a computer system as it
(A) Consumes less power (B) has higher speed
(C) has lower cell density (D) needs refreshing circuitry
Ans: B

25. In signed magnitude binary division, if the dividend is (11100) 2 and divisor is (10011) 2 then the result is
(A) (00100) 2 (B) (10100) 2 (C) (11001) 2 (D) (01100) 2
Ans: B

26. Virtual memory consists of
(A) Static RAM (B) Dynamic RAM
(C) Magnetic memory (D) None of these
Ans: A

27. In a program using subroutine call instruction, it is necessary
(A) initialise program counter (B) Clear the accumulator
(C) Reset the microprocessor (D) Clear the instruction register
Ans: D

28. A Stack-organised Computer uses instruction of
Ans: C

29. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be
(A) 11 bits (B) 21 bits (C) 16 bits (D) 20 bits
Ans: C

30. A-Flip Flop can be converted into T-Flip Flop by using additional logic circuit
(A) n TQD =• (B) T D = (C) D = T . Q n (D) n TQD =⊕
Ans: D

31. Logic X-OR operation of (4ACO) H & (B53F) H results
(A) AACB (B) 0000 (C) FFFF (D) ABCD
Ans: C

32. When CPU is executing a Program that is part of the Operating System, it is said to be in
(A) Interrupt mode (B) System mode (C) Half mode (D) Simplex mode
Ans: B

33. An n-bit microprocessor has
(A) n-bit program counter (B) n-bit address register
(C) n-bit ALU (D) n-bit instruction register
Ans: D

34. Cache memory works on the principle of
(A) Locality of data (B) Locality of memory
(C) Locality of reference (D) Locality of reference & memory
Ans: C

35. The main memory in a Personal Computer (PC) is made of
(A) cache memory. (B) static RAM
(C) Dynamic Ram (D) both (A) and (B)
Ans: D

36. In computers, subtraction is carried out generally by
(A) 1’s complement method (B) 2’s complement method
(C) signed magnitude method (D) BCD subtraction method
Ans: B

37. PSW is saved in stack when there is a
(A) interrupt recognised (B) execution of RST instruction
(C) Execution of CALL instruction (D) All of these
Ans: A

38. The multiplicand register & multiplier register of a hardware circuit implementing booth’s algorithm have (11101) & (1100). The result shall be
(A) (812) 10 (B) (-12) 10 (C) (12) 10 (D) (-812) 10
Ans: A

39. The circuit converting binary data into decimal is
(A) Encoder (B) Multiplexer (C) Decoder (D) Code converter
Ans: D

40. A three input NOR gate gives logic high output only when
(A) one input is high (B) one input is low
(C) two input are low (D) all input are high
Ans: D

## Set:- 3 MCQ on Computer Architecture

41. n bits in operation code imply that there are ___________ possible distinct operators
(A) 2n (B) 2n (C) n/2 (D) n2
Ans: B

42. _________ register keeps tracks of the instructions stored in a program stored in memory.
(A) AR (Address Register) (B) XR (Index Register)
(C) PC (Program Counter) (D) AC (Accumulator)
Ans: C

43. Memory unit accessed by content is called
(A) Read only memory (B) Programmable Memory
(C) Virtual Memory (D) Associative Memory
Ans: D

44. ‘Aging registers’ are
(A) Counters which indicate how long ago their associated pages have been referenced.
(B) Registers which keep track of when the program was last accessed.
(C) Counters to keep track of last accessed instruction.
(D) Counters to keep track of the latest data structures referred.
Ans: A

45. The instruction ‘ORG O’ is a
(A) Machine Instruction. (B) Pseudo-instruction.
(C) High-level instruction. (D) Memory instruction.
Ans: B

46. Translation from the symbolic program into Binary is done in
(A) Two passes. (B) Directly (C) Three passes. (D) Four passes.
Ans: A

47. A floating-point number that has an O in the MSB of the mantissa is said to have
(A) Overflow (B) Underflow (C) Important number (D) Undefined
Ans: B

48. The BSA instruction is
(A) Branch and store accumulator (B) Branch and save the return address
(C) Branch and shift address (D) Branch and show accumulator
Ans: B

49. State whether True or False.
(i) Arithmetic operations with fixed-point numbers take a longer time for execution as compared to floating-point numbers.
Ans: True.
(ii) An arithmetic shift left multiplies a signed binary number by 2.
Ans: False.

50. Logic gates with a set of input and outputs are an arrangement of
(A) Combinational circuit (B) Logic circuit (C) Design circuits (D) Register
Ans: A

51. MIMD stands for
(A) Multiple instruction multiple data (B) Multiple instruction memory data
(C) Memory instruction multiple data (D) Multiple information memory data
Ans: A

52. A k-bit field can specify any one of
(A) 3k registers (B) 2k registers
(C) K2 registers (D) K3 registers
Ans: B

53. The time interval between adjacent bits is called the
(A) Word-time (B) Bit-time (C) Turn around time (D) Slice time
Ans: B

54. A group of bits that tell the computer to perform a specific operation is known as
(A) Instruction code (B) Micro-operation (C) Accumulator (D) Register
Ans: A

55. The load instruction is mostly used to designate a transfer from memory to a processor register known as
(A) Accumulator (B) Instruction Register
(C) Program counter (D) Memory address Register
Ans: A
56. The communication between the components in a microcomputer takes place via the address and
(A) I/O bus (B) Data bus (C) Address bus (D) Control lines
Ans: B

57. An instruction pipeline can be implemented by means of
(A) LIFO buffer (B) FIFO buffer (C) Stack (D) None of the above
Ans: B

58. The data input command is just the opposite of a
(A) Test command (B) Control command (C) Data output (D) Data channel
Ans: C

59. A microprogram sequencer
(A) generates the address of next microinstruction to be executed.
(B) generates the control signals to execute a microinstruction.
(C) sequentially averages all microinstructions in the control memory.
(D) enables the efficient handling of a microprogram subroutine.
Ans: A

60. A binary digit is called a
(A) Bit (B) Byte (C) Number (D) Character
Ans: A

## Set:- 4 MCQ on Computer Architecture

61. A flip-flop is a binary cell capable of storing information of
(A) One bit (B) Byte (C) Zero bit (D) Eight-bit
Ans: A

62. The operation executed on data stored in registers is called
(A) Macro-operation (B) Micro-operation
(C) Bit-operation (D) Byte-operation
Ans: B

63. MRI indicates
(A) Memory Reference Information. (B) Memory Reference Instruction.
(C) Memory Registers Instruction. (D) Memory Register information
Ans: B

64. A self-contained sequence of instructions that performs a given computational task is called
(A) Function (B) Procedure (C) Subroutine (D) Routine
Ans: A

65. Micro instructions are stored in control memory groups, with each group specifying a
(A) Routine (B) Subroutine (C) Vector (D) Address
Ans: A

66. An interface that provides a method for transferring binary information between internal storage and external devices is called
(A) I/O interface (B) Input interface (C) Output interface (D) I/O bus
Ans: A

67. The status bit is also called
(A) Binary bit (B) Flag bit (C) Signed bit (D) Unsigned bit
Ans: B

68. An address in the main memory is called
Ans: A

69. If the value V (x) of the target operand is contained in the address field itself, the addressing mode is
(A) immediate. (B) direct. (C) indirect. (D) implied.
Ans: B

70. can be represented in a signed magnitude format and in a 1’s complement format as
(A) 111011 & 100100 (B) 100100 & 111011
(C) 011011 & 100100 (D) 100100 & 011011
Ans: A

71. The instructions which copy information from one location to another either in the processor’s internal register set or in the external main memory are called
(A) Data transfer instructions. (B) Program control instructions.
(C) Input-output instructions. (D) Logical instructions.
Ans: A

72. A device/circuit that goes through a predefined sequence of states upon the application of input pulses is called
(A) register (B) flip-flop (C) transistor. (D) counter.
Ans: D

73. The performance of cache memory is frequently measured in terms of a quantity called
(A) Miss ratio. (B) Hit ratio. (C) Latency ratio. (D) Read ratio.
Ans: C

74. The information available in a state table may be represented graphically in a
(A) simple diagram. (B) state diagram. (C) complex diagram. (D) data flow diagram.
Ans: B

75. Content of the program counter is added to the address part of the instruction in order to obtain the effective address is called.
(C) register mode. (D) implied mode.
Ans: A

76. An interface that provides I/O transfer of data directly to and forms the memory unit and peripheral is termed as
(A) DDA. (B) Serial interface. (C) BR. (D) DMA.
Ans: D

77. The 2s complement form (Use 6-bit word) of the number 1010 is
(A) 111100. (B) 110110. (C) 110111. (D) 1011.
Ans: B

78. A register capable of shifting its binary information either to the right or the left is called a
(A) parallel register. (B) serial register. (C) shift register. (D) storage register.
Ans: C

79. What is the content of Stack Pointer (SP)?
(A) Address of the current instruction (B) Address of the next instruction
(C) Address of the top element of the stack (D) Size of the stack.
Ans: C

80. Which of the following interrupt is non-maskable
(A) INTR. (B) RST 7.5. (C) RST 6.5. (D) TRAP.
Ans: D

## Set:- 5 MCQ on Computer Architecture

81. Which of the following is the main memory
(A) Secondary memory. (B) Auxiliary memory.
(C) Cache memory. (D) Virtual memory.
Ans: C

82. Which of the following are not machine instructions
(A) MOV. (B) ORG. (C) END. (D) (B) & (C)
Ans: D

83. In Assembly language programming, a minimum number of operands required for instruction is/are
(A) Zero. (B) One. (C) Two. (D) Both (B) & (C) .
Ans: A

84. The maximum addressing capacity of a microprocessor which uses 16-bit database & 32-bit address base is
(A) 64 K. (B) 4 GB. (C) both (A) & (B) . (D) None of these.
Ans: B

85. The memory unit that communicates directly with the CPU is called the
(A) main memory (B) Secondary memory
(C) shared memory (D) auxiliary memory.
Ans: A

86. The average time required to reach a storage location in memory and obtain its contents is called
(A) Latency time. (B) Access time.
(C) Turnaround time. (D) Response time.
Ans: B

State True or False

87. A byte is a group of 16 bits.
Ans: False

88. A nibble is a group of 16 bits.
Ans: False

89. When a word is to be written in associative memory, the address has got to be given.
Ans: False

90. When two equal numbers are subtracted, the result would be ______and not_________.

Ans: +ZERO, -ZERO.

91. A ___________development system and an ______are essential tools for writing large assembly language programs.
Ans: Microprocessor, assembler

92. In an operation performed by the ALU, carry bit is set to 1 if the end carry C 8 is ________. It is cleared to 0 (zero) if the carry is ______ _______.
Ans: One, zero

93. A successive A/D converter is
(A) a high-speed converter. (B) a low-speed converter.
(C) a medium speed converter. (D) none of these.
Ans: C

94. When necessary, the results are transferred from the CPU to the main memory by
(A) I/O devices. (B) CPU. (C) shift registers. (D) none of these.
Ans: C

96. A combinational logic circuit which sends data coming from a single source to two or more separate destinations is
(A) Decoder. (B) Encoder. (C) Multiplexer. (D) Demultiplexer.
Ans: D

97. In which addressing mode the operand is given explicitly in the instruction
(A) Absolute (B) Immediate (C) Indirect (D) Direct
Ans: B

98. A stack organised computer has
Ans: D

99. A Program Counter contains a number 825 and addresses part of the instruction contains the number 24. The effective address in the relative address mode, when an instruction is read from the memory is
(A) 849. (B) 850. (C) 801. (D) 802.
Ans: B

100.  A page fault
(A) Occurs when there is an error in a specific page.
(B) Occurs when a program accesses a page of main memory.
(C) Occurs when a program accesses a page not currently in main memory.
(D) Occurs when a program accesses a page belonging to another program.
Ans: C.

Apart from this MCQ on Computer Architecture for competitive exams, solving online test will help you to fetch some extra marks. Here are some of the useful links where you can find the best study materials and Books on Computer Awareness for competitive exams.

### Books

A good book can help you to crack any competitive examination. You can buy these books on Computer Awareness to score best and practise more sets on MCQ on Computer Architecture.